Hardware in the Loop for Renewable systems with SoC platforms
City University of Hong Kong is organizing a School for young researchers, technically sponsored by ESoC Technical Committee of IES IEEE.
The event provides Master and PhD students, lecturer, researchers and engineers from academia and industry the opportunity to design/implement and hardware/software co-simulate a renewable energy system.
HILRES’23 aims to providing a three-day design from scratch experience of a bare-metal SoPC based Hardware in the Loop platform to model, simulate and control a complete Photovoltaic (PV) system using various design methodologies on low-cost SoC platforms.
Key Activities
Here is the provisional schedule for HILRES School. This schedule is subject to minor changes that will be announced later.
Wednesday, June 19th, 2024
- Fundamentals of a photovoltaic system.
- Controlling a photovoltaic system.
- Matlab/Simulink modelling and simulation of a photovoltaic system.
- SoC FPGA Hardware/software co-design of a photovoltaic system with PYNQ boards (D/A and A/D converters, PWM), Power converters on-chip modelling.
Thursday, June 20th, 2024
- SoC & Zynq Architecture (heterogeneous SoC, Processor System, FPGA, architecture and interfacing).
- VHDL fundamentals.
- FPGA-based for Ac drive applications.
- Core to Core Communication (synchronous and asynchronous communications, interface definition and selection, internal communication between different processor cores).
- SoC FPGA Hardware/software co-design of a photovoltaic system with PYNQ boards (Dual-core ARM Cortex-A9 processor, I/O, Timers, interrupts).
Friday, June 21th, 2024
- Co-simulation and FPGA in the Loop simulation.
- Hardware in the loop fundamentals.
- Designing with the Zynq (hardware design definition in Vivado using IP Integrator, custom IP, software development using Vitis).
Keynote speakers, lectures
- Dr. Alin Tisan, Royal Holloway University of London, UK (SoC, VHDL design)
- Prof. Mickael Hilairet, Ecole Centrale de Nantes / LS2N, FR, (PV system modelling and control).
- Dr. Lahoucine Id-khajine, Cergy-Pontoise University, FR, (FPGA acceleration, Design tools)
- Prof. Tarek Ould-Bachir, Polytechnique Montréal, CA (Power converters on-chip modelling)
Events daily schedule
| Time | Event |
|---|---|
| 8:30 am - 9:00 am | Breakfast |
| 9am - 10:30am | HILRES Session 1 |
| 10:30 - 11am | Coffee break |
| 11am - 12pm | HILRES Session 2 |
| 12pm - 1pm | Lunch |
| 1:00 - 2:30pm | HILRES Session 3 |
| 2:30pm - 3pm | Coffee break |
| 3pm - 5pm | HILRES Session 4 |
Registration
Please register via our online application form. There will be only 20 tickets available, given on a first-come, first-served basis.